AMD Launches Vitis Hardware in the Loop for Versal Silicon Validation
AMD has unveiled its Vitis Hardware in the Loop (Vitis HIL) solution, designed to enhance system-level validation for its Versal adaptive SoCs and FPGAs directly from MATLAB or Python environments. This approach aims to bridge the gap between simulation and hardware testing, leveraging real silicon for faster and more precise verification. The announcement was made in a blog post by Udayan Sinha, published on October 7, 2026.
Evidence and context
Vitis HIL integrates existing MATLAB and Python test environments with the validation process for AMD Versal systems, which combine AI engines, programmable logic, and embedded processing. This allows engineering teams to reuse familiar testbenches, stimulus generation, and analysis workflows, saving time and resources compared to rebuilding tools for hardware-specific testing.
The solution supports evaluation on physical silicon using development kits like the Versal AI Core VCK190 and Versal AI Edge VEK280. These kits target applications ranging from aerospace signal processing to automotive and industrial edge workloads. By running designs on actual hardware, Vitis HIL captures real-world pipeline latency, fixed-point rounding, and memory effects that simulation alone may not reveal. According to AMD, this capability is particularly valuable for validating complex designs such as DSP algorithms and AI Engine computations that require deterministic performance and spectral fidelity.
Vitis HIL's workflow is split into two phases. An initial setup phase configures the hardware and generates a bootable image, while an iterative test phase enables repeated validation as the design evolves. This separation minimizes the need for manual intervention and supports integration into automated workflows or continuous integration pipelines. AMD emphasizes that Vitis HIL is complementary to traditional simulation, extending its utility when higher performance or hardware fidelity is required.
The inclusion of Vitis HIL in the AMD Vitis 2026.1 platform underscores the company's commitment to streamlining the development process for engineers working on heterogeneous systems. Documentation and practical examples, such as a polyphase channelizer demo showcased on Hackster.io, provide further guidance for adopting this tool.
AMD's market position has been bolstered by its focus on adaptive computing. As of October 8, 2026, the company's market capitalization stands at $1.071 trillion, with its stock trading at $645.86, reflecting a 0.55% decline over the previous 24 hours. While this market data does not directly tie to the Vitis HIL announcement, it demonstrates the scale of AMD's operations in high-performance and adaptive computing sectors.
By introducing Vitis HIL, AMD aims to address critical verification challenges faced by algorithm engineers, signal processing experts, FPGA architects, and system integrators. With its ability to validate real-world performance on silicon, the tool could accelerate the design-to-deployment timeline for Versal-based systems.